Update SEC_BOOT_CFG5 register size to 32 bits#25
Update SEC_BOOT_CFG5 register size to 32 bits#25ayodejiige wants to merge 1 commit intoOpenDevicePartnership:mainfrom
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Pull Request Overview
This PR updates the SEC_BOOT_CFG5 register definition to use 32 bits instead of 16 bits, aligning the implementation with the correct hardware specification.
- Updated register size from 16 bits to 32 bits in both JSON configuration and generated Rust code
- Modified internal storage from 2-byte to 4-byte array to accommodate the larger size
- Updated all related type conversions and constants to maintain consistency
Reviewed Changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated no comments.
| File | Description |
|---|---|
| libs/imxrt-rom/src/registers/device.rs | Updated Rust struct implementation to use 4-byte array and 32-bit size constant |
| libs/imxrt-rom/registers.json | Changed register size specification from 16 to 32 bits |
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This particular register is 16 bits however. Probably the method to write OTP fuses has an issue instead. 
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The problem is that for writing the register I have used ec-slimloader/libs/imxrt-rom/src/registers.rs Lines 114 to 119 in 76d6f5c |
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Fixed in #26. You can close this PR. |
We have a single device-driver definition of the OTP fuse registers, but can access them both from shadow registers, as well as from the OTP ROM API. In the OTP ROM API implementation writing to registers smaller than 32 bits did not do anything. See #25. This is due to calling `chunks_exact` with a size of 4, which does not yield any chunk if the remaining buffer cannot fit exactly that chunk: https://github.com/OpenDevicePartnership/ec-slimloader/blob/76d6f5cc2a422e0aa0a1fcf23a5c81c251276f5a/libs/imxrt-rom/src/registers.rs#L114-L119 This PR streamlines how the OTP words are accessed between OTP ROM API and shadow registers, and adds a few tests to validate that it does so correctly.
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